This project advances a full formal-methods workflow from high-level differential dynamic logic models to executable PLC controller logic, with explicit links that preserve safety guarantees across design and runtime.
The public materials center on modular verification, monitor synthesis, and translation methods that connect model-level proofs with implementation artifacts used in realistic ICS settings.
The work builds on and extends prior HyPLC efforts, and informs follow-on work such as HyTwin for digital-twin-based security interventions.